Doped polycrystalline silicon ("poly-Si") is most commonly used as a gate electrode in metal oxide semiconductor ("MOS")-based circuits. Due to the ever shrinking size of electrical components in general, MOS devices have also become smaller, and as their size has decreased, the resistivity of the poly-Si, unfortunately, has also increased, which, in turn, has affected the device RC-delay ("RC"). This is disadvantageous to the device because RC delays caused by high sheet resistance between 20-100 ohms/square of poly-Si runners, limit the performance of the integrated circuits with n.sup.+ doped poly-Si, and their performance also deteriorates as the length of these runners increases.
To overcome the problems associated with this increased resistance, a polycide stack ("poly-Si/silicide") is extensively used. Typically, the poly-Si is clad with a low-resistivity silicide such that the sheet resistance of the polycide is between 5-10 ohms/sq from 20-100 ohms/sq without the silicide. The ratio of silicon to metal (Si/M) of the silicide is important to maintain in the range of about 2:1 to about 2.8:1 because if the Si/M ratio falls below this level, the polycide becomes metal rich, which affects the resistivity within the poly-Si gate in an undesirable manner.
Physical vapor deposition ("PVD") is typically used to deposit this silicide layer because the PVD technique produces a smoother, amorphous-type barrier, as compared to the chemical vapor deposition ("CVD") films, which are rougher and crystalline or nano-crystalline. Typically, silicon sputters differentially from the metal in PVD targets, and so, to compensate for the correct film stoichiometry, the target material and the film generally contains excess Si. Moreover, a silicide target shows a drop in silicon to metal (Si/M) ratio as a function of its useful life. Films deposited from a continually eroding target will show a progressive decrease in the Si/M ratio. When the film composition drops below the required 2:1 ratio, the target is discarded, often with significant material wasted, thereby, adding to increase cost per device per wafer.
Therefore, what is needed in the art is a method that provides an in-situ intermediate layer of PVD amorphous silicon when the useful life of the target, as determined by the Si/M ratio, falls below a predetermined level, to thereby prolong the useful life of the target and decrease the overall cost of the semiconductor device.